In FLASH and XFEL the field parameters are evaluated separately for every cavity and after demodulation in down-converters the phases and amplitudes are extracted. This information needs to be aggregated and processed to calculate the correction that should be applied to the EM field before the arrival of the next bunch. The actuation is done using vector modulator, that performs quadrature modulation of reference clock signal and feeds it to RF power amplifiers.

One of the most important components of the system described above is the Low Level Radio Frequency (LLRF) controller. This device is responsible for concentrating and processing signals from various feedback sources, calculating the required correction and providing other components with the information on current field parameters. Such a controller was developed in the Department of Microelectronics and Computer Science (DMCS) of the Technical University of Lodz in cooperation with Deutsches Elektronen-Synchrotron (DESY).

The controller board is designed according to the Advanced Mezzanine Card (AMC) specification with the intention to maintain the compatibility with MTCA.4 specification, being currently actively developed by PICMG. It is implemented as a double width AMC module and adapted to connect directly to the vector modulator realized as a Rear Transition Module (RTM). Such an organization provides short and reliable links between these two systems.

The Image Acquisition Module is designed to observe the plasma inside the thermonuclear reactor of the ITER project. The ITER Instrumentation and Control (I&C) system is supposed to include about 20 video cameras with frame sampling frequencies of 1 kHz and approximately 200 high-resolution imaging devices providing data with throughput reaching almost 7 Gb/s. The operates in the MTCA chassis, hence it conforms to both MTCA and AMC specifications. Fulfillment of the specification requirements benefits in high Reliability, Accessibility and Serviceability (RAS) of the final product. Despite that machine vision plays an important role in many industrial processes, there are no COTS high-speed video acquisition AMC cards available. The developed Image Acquisition Module (IAM) is composed of two boards: the off-the-shelf AMC processing module and the custom built frame grabber extension card.

The universal module for video stream acquisition from fast cameras with Camera Link interface was designed as part of the PCIe Image Acquisition Module. The first version of the Camera Link standard defines three configurations: Base, Medium and Full. The developed module supports all of them achieving transmission speeds up to 5.44 Gb/s for raw image data in the Full configuration. The module is designed according to FPGA Mezzanine Card (FMC) standard and can cooperate with carrier boards containing High-Pin Count (HPC) version of the connector. The module was tested with the TEWS TAMC-641 module.

Each of the data transmission lines carries data with bit rate reaching almost 600 Mb/s. Twelve such a lines have to be routed to the dedicated deserializer circuits. The tracks have to be well equalized and tuned to avoid the phase skew. The low-noise continuous reference planes for the data signals and clocks are required. The DS90CR288A form Texas Instruments is a single-chip Channel Link receiver. It provides the module with the most important components: the PLL and deserializer block. The built-in loop attenuates the clock jitter and provides a 595 MHz clock for data deserialization. Each deserializer drives 28 LVCMOS data lines and provides a slow clock signal for synchronization (up to 85 MHz). The recovered signals are converted to LVDS and provided to the FMC connector.

The PTM-1588 is a MTCA.4-compliant timing module. The device can act as master or slave of the IEEE 1588 Precise Time Protocol (PTP). The temperature-compensated voltage-controlled crystal oscillator (TCVCXO) is used as reference clock. Using information obtained through the Ethernet connection the oscillator frequency is tuned to keep the generated clock in sync with grand master clock. The module offers 10 MHz or 100 MHz output clock on the front-panel SMB connector as well as on the AMC connector. The other three front-panel SMB connectors may be used for trigger/event inputs or outputs. The module can also access the eight parallel M-LVDS buses on the MTCA.4 compatible backplane. Optionally the device may contain Low-Pin Count FMC (FPGA Mezzanine Card) connector.

Testing of the analog full-custom ASIC requires dedicated test bench. The DUT contains four charge-sensitive channels with a variety of biasing voltages and currents. The data are read using serial bus operating at 100 MHz. Device settings are accessible via SPI bus. All those signals together with power supplies and test pulses of adjustable level are supplied by the developed test bench.

The test bench uses the STM32F4-DISCOVERY starter kit with ARM Cortex-M4 processor running at 100 MHz (mounted under the main board). The processor system provides computing power, clocks and synchronized triggers. The main board offers power supplies, CPLD circuit and 24 DAC channels for setting the bias currents and voltages. The CPLD circuit is supplied with clock, trigger and data signals and can be used for capturing the data outputted by the DUT. It is connected to the processor module with 8-bit parallel bus with several control signals.

The DUT is located on the small daughter board. The chip is directly bonded to the PCB. The daughter board has the pulse shaping circuity, power supply filters and easily accessible test points. The chip is covered by another PCB to protect if from possible mechanical damage.

The device automates a medical study, which is commonly used to assess the dysfunction of the cervical spine and for its rehabilitation. The adopted method of diagnosis is based on determining the scope and dynamics of the motion that the patient is able to perform with his head. Currently, the test is performed by attaching a laser pointer to the patient's head, and observing how he follows the defined shapes with the laser spot. This method requires doctor to stay strongly focused for about ten minutes, in which he assesses the quality and time of completion of subsequent tasks. Estimation of the accuracy, with which the examined is able to operate the spot, the definition of the covered scope of the screen and measurement of the time are tasks, that can be successfully performed by the computer. Reduction of human engagement in the process of the data capture can make the assessment more precise and repeatable. Computer storage of the results will in the future facilitate tracking progress in rehabilitation and will help design new exercises tailored to the individual patient's needs.

The measuring device is attached to the patient's head in the same way as the laser pointer was. After the start of the study, it tracks its own position with the use of integrated sensors of the linear and angular acceleration. The system is also equipped with the magnetometer, which may help find the device's absolute orientation in space. Using information from the sensors, the computer determines the angle of elevation of the head and angle of its rotation around the vertical axis. The cursor, which is controlled by the patient, is displayed along with the shapes required for the study using a multimedia projector. Because both, the spot position and the geometry of the displayed paths are stored in computer memory, it is possible to quickly and accurately determine how far from the defined shape is the pointer located. It is also possible to record time needed for the spot to pass between designated points, which allows measurement of not only the precision but also the dynamics of the motion.